This invention relates to a low-power low-voltage buffer with a half-latch. More particularly, this invention relates to a half-latch low-voltage buffer design that may provide increased speed without dramatically increasing power consumption.
Typical buffer designs consist of an NMOS passgate, two inverters, and a half-latch. The NMOS passgate serves as a switch to selectably pass or block voltage from the inverters. Typical NMOS passgates may not be able to pass full voltage levels. A typical NMOS passgate may reduce the passed voltage level by an amount approximately equal to the threshold voltage (VT) of the transistor. The half-latch, in response to the output of one of the inverters, may pull up the output of the NMOS passgate to the full voltage level.
When operated with high voltage levels, the voltage reduction of the NMOS passgate may not significantly affect the performance of the buffer. However, when operated with lower voltage levels, the voltage reduction of the NMOS passgate may slow down or prevent the buffer from passing the input signal.
One approach used to increase the speed of low-voltage buffer circuits is to reduce the threshold voltage of the NMOS passgates. This minimizes the reduction in the voltage level by the passgate and increases the speed of the buffer. One drawback to using lower threshold voltage NMOS passgates is increased leakage currents. The lower the threshold voltage of the NMOS passgates, the greater the leakage current passing through the passgates. The greater the leakage currents passing through the passgates, the higher the power consumption of the buffer circuit. Thus, when adjusting the threshold voltage of the NMOS passgates there is a tradeoff between increased speed and increased power consumption.